Field of the Invention
The present invention relates to an assembly for associative memories and to a high-performance circuit intended for multiprocessor systems having two hierarchically arranged memory levels.
A related associative memory is disclosed in a copending application Ser. No. 785,234, filed Apr. 6, 1977, by Daniel Vinot, now U.S. Pat. No. 4,128,899 the entire disclosure of which is hereby incorporated by reference.
The use of associative memories as memory masks with multiprocessors creates problems from the point of view of the software which, in order to ensure the validity of the information contained in the memories, has constantly to update a validity bit associated with each addressed location in a circuit external to the memories. The problem is all the more complicated because of the numerous write operations which are performed in the auxiliary memory and which may be initiated by any processor. The management involved, which is the responsibility of the software, takes time.
During a write operation, each address is transmitted simultaneously to all the masks of the system and a search is made. If the search is successful, the corresponding location is indicated as requiring invalidation. The frequency of the invalidating operations increases with the number of processors. If a normal search operation and an invalidating operation cannot be performed simultaneously, priority is given to the invalidating function and this inevitably reduces the performance of the computer. This problem exists in particular in cases where a plurality of processors share the same auxiliary memory via a plurality of masks. If a processor performs a write operation at location Y in the auxiliary memory and if mask O has a copy of this location Y, this copy becomes out of date and thus incorrect and needs to be invalidated. The arrangement which is the subject of the present invention allows simultaneous and independent searches for a local user and for a possible invalidation. It prevents any interference between normal running and the invalidation function as used in the specification, the term "normal" is not an invalidation mode and is used to distinguish between an invalidation mode and a normal processing running mode.